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"25-Gb/s clock and data recovery IC using latch-load combined with CML ..."

Tomonori Tanaka et al. (2017)

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DOI: 10.1109/ISCAS.2017.8050696

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka:
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. ISCAS 2017: 1-4

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