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"Modelling and Analysis of Lower Metal On-Chip Interconnects Using Physical ..."

Aditya Kulkarni, Iteesh V. A, Sahith S. R (2019)

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DOI: 10.1109/iSES47678.2019.00087

access: closed

type: Conference or Workshop Paper

metadata version: 2020-04-26

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Aditya Kulkarni, Iteesh V. A, Sahith S. R:
Modelling and Analysis of Lower Metal On-Chip Interconnects Using Physical Fabrication Parameters. iSES 2019: 350-354

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