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"A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit ..."

Seiji Miura, Kazushige Ayukawa, Takao Watanabe (2001)

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DOI: 10.1145/383082.383183

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Seiji Miura, Kazushige Ayukawa, Takao Watanabe:
A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. ISLPED 2001: 358-363

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