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"Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder ..."
Alejandro F. González et al. (2000)
- Alejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder:
Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. ISMVL 2000: 323-330
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