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"Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for ..."

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (2004)

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DOI: 10.1109/ISQED.2004.1283703

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/isqed/IizukaIA04
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED 2004: 377-380

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