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"A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage ..."

Koji Nii et al. (2013)

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DOI: 10.1109/ISQED.2013.6523648

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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  - conf/isqed/NiiYFTIMM13
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  - https://dblp.org/rec/conf/isqed/NiiYFTIMM13
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda:
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED 2013: 438-441

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