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"Impact of Interconnect Process Variations on Memory Performance and Design."

Andres Teene et al. (2005)

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DOI: 10.1109/ISQED.2005.63

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/isqed/TeeneDCBR05
Andres Teene, Bob Davis, Ruggero Castagnetti, Jeff Brown, S. Ramesh:
Impact of Interconnect Process Variations on Memory Performance and Design. ISQED 2005: 694-699

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