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"A process-variation-tolerant dual-power-supply SRAM with ..."

Osamu Hirabayashi et al. (2009)

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DOI: 10.1109/ISSCC.2009.4977506

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  dblp key:
  - conf/isscc/HirabayashiKSTKSKFFNSKY09
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/HirabayashiKSTKSKFFNSKY09
Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe:
A process-variation-tolerant dual-power-supply SRAM with 0.179µm² Cell in 40nm CMOS using level-programmable wordline driver. ISSCC 2009: 458-459

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