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"A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with ..."

Win-San Khwa et al. (2018)

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DOI: 10.1109/ISSCC.2018.8310401

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-26

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  - conf/isscc/KhwaCLSYSLCLYC18
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Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang:
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC 2018: 496-498

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