"A 32-core RISC microprocessor with network accelerators, power management ..."

Brian Miller et al. (2012)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2012.6176877

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/MillerBKKMSKVYLHSKPHCYXMCSABVTLKFJ12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/MillerBKKMSKVYLHSKPHCYXMCSABVTLKFJ12
Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott E. Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain:
A 32-core RISC microprocessor with network accelerators, power management and testability features. ISSCC 2012: 58-60

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.