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"A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing ..."

Hidehiro Shiga et al. (2009)

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DOI: 10.1109/ISSCC.2009.4977509

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-15

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  dblp key:
  - conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09
Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. ISSCC 2009: 464-465

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