"A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC ..."

He Gong Wei et al. (2011)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2011.5746276

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/WeiCCSSMM11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/WeiCCSSMM11
He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 0.024mm² 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC 2011: 188-190

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.