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"3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a ..."

John J. Wuu et al. (2022)

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DOI: 10.1109/ISSCC42614.2022.9731565

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-10

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  dblp key:
  - conf/isscc/WuuACDJJSSWN22
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  - https://dblp.org/rec/conf/isscc/WuuACDJJSSWN22
John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger:
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. ISSCC 2022: 428-429

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