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"8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed ..."

Danfeng Xu et al. (2021)

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DOI: 10.1109/ISSCC42613.2021.9366063

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-03

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  dblp key:
  - conf/isscc/XuKLCCMZLLJPSTM21
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  - https://dblp.org/rec/conf/isscc/XuKLCCMZLLJPSTM21
Danfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan:
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. ISSCC 2021: 134-136

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