"10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and ..."

Dingxin Xu et al. (2024)

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DOI: 10.1109/ISSCC49657.2024.10454284

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type: Conference or Workshop Paper

metadata version: 2024-07-16

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Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada:
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. ISSCC 2024: 192-194

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