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"Activity-Aware Registers Placement for Low Power Gated Clock Tree ..."

Weixiang Shen et al. (2007)

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DOI: 10.1109/ISVLSI.2007.20

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/isvlsi/ShenCHH07
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  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/ShenCHH07
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388

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