"Efficient Fault Simulation of CMOS Circuits with Accurate Models."

Zeev Barzilai et al. (1986)

> Home

Details and statistics

DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2006-07-11

- no documents available
- export record
  dblp key:
  - conf/itc/BarzilaiCINRRS86
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/itc/BarzilaiCINRRS86
Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman:
Efficient Fault Simulation of CMOS Circuits with Accurate Models. ITC 1986: 520-529

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.