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"DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O ..."

Sergej Deutsch et al. (2012)

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DOI: 10.1109/TEST.2012.6401569

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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  dblp key:
  - conf/itc/DeutschKCMSGCMLM12
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  persistent URL:
  - https://dblp.org/rec/conf/itc/DeutschKCMSGCMLM12
Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen:
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC 2012: 1-10

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