"Testing 3D chips containing through-silicon vias."

Erik Jan Marinissen, Yervant Zorian (2009)

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DOI: 10.1109/TEST.2009.5355573

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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Erik Jan Marinissen, Yervant Zorian:
Testing 3D chips containing through-silicon vias. ITC 2009: 1-11

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