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"FPGA versus GPU for Speed-Limit-Sign Recognition."

Matthew Yih et al. (2018)

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DOI: 10.1109/ITSC.2018.8569462

access: closed

type: Conference or Workshop Paper

metadata version: 2018-12-12

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  dblp key:
  - conf/itsc/YihOOM18
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  - https://dblp.org/rec/conf/itsc/YihOOM18
Matthew Yih, Jeffrey M. Ota, John D. Owens, Pinar Muyan-Özçelik:
FPGA versus GPU for Speed-Limit-Sign Recognition. ITSC 2018: 843-850

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