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ORCID"A high speed BIST architecture for DDR-SDRAM testing."
Sheng-Chih Shen et al. (2005)
- Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee:
A high speed BIST architecture for DDR-SDRAM testing. MTDT 2005: 52-57
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