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"A systematic approach to reducing semiconductor memory test time in mass ..."
Jen-Chieh Yeh et al. (2005)
- Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu
, Chih-Tsun Huang, Chao-Hsun Chen:
A systematic approach to reducing semiconductor memory test time in mass production. MTDT 2005: 97-102
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