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"Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain."

Nahid M. Hossain et al. (2017)

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DOI: 10.1109/MWSCAS.2017.8053215

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-26

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Nahid M. Hossain, Arif Iqbal, Hemanshu Shishupal, Masud H. Chowdhury:
Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain. MWSCAS 2017: 1485-1488

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