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"Novel SRAM bias control circuits for a low power L1 data cache."

Azam Seyedi et al. (2012)

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DOI: 10.1109/NORCHP.2012.6403113

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-02

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  dblp key:
  - conf/norchip/SeyediACUV12
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  - https://dblp.org/rec/conf/norchip/SeyediACUV12
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Novel SRAM bias control circuits for a low power L1 data cache. NORCHIP 2012: 1-6

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