"Integrated Circuit and System Design. Power and Timing Modeling, ..."

Lars Svensson, José Monteiro (2009)

> Home

Details and statistics

DOI: 10.1007/978-3-540-95948-9

access: closed

type: Editorship

metadata version: 2022-02-23

- view
  authority control:
- export record
  dblp key:
  - conf/patmos/2008
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/patmos/2008
Lars Svensson, José Monteiro:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers. Lecture Notes in Computer Science 5349, Springer 2009, ISBN 978-3-540-95947-2 [contents]

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.