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"A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra ..."

Wei Zhou et al. (2016)

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DOI: 10.1007/978-3-319-48890-5_46

access: closed

type: Conference or Workshop Paper

metadata version: 2021-09-01

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  dblp key:
  - conf/pcm/ZhouNLZY16
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Wei Zhou, Yue Niu, Xiaocong Lian, Xin Zhou, Jiamin Yang:
A Stepped-RAM Reading and Multiplierless VLSI Architecture for Intra Prediction in HEVC. PCM (1) 2016: 469-478

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