"VCEGAR: Verilog CounterExample Guided Abstraction Refinement."

Himanshu Jain et al. (2007)

Details and statistics

DOI: 10.1007/978-3-540-71209-1_45

access: open

type: Conference or Workshop Paper

metadata version: 2018-06-26

a service of  Schloss Dagstuhl - Leibniz Center for Informatics