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"A unified Verilog-A compact model for lateral Si nanowire (NW) FET ..."

Om. Prakash et al. (2016)

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DOI: 10.1109/ISVDAT.2016.8064852

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-17

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Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas:
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. VDAT 2016: 1-6

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