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"High speed DDR2/3 PHY and dual CPU core design for 28nm SoC."
Kevin Ho et al. (2012)
- Kevin Ho, Tsung-Yi Chou, Po-Kai Chen, David J. Liou:
High speed DDR2/3 PHY and dual CPU core design for 28nm SoC. VLSI-DAT 2012: 1-5
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