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"A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for ..."

Xiaohua Huang et al. (2018)

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DOI: 10.1109/VLSI-DAT.2018.8373226

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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Xiaohua Huang, Han Liu, Woogeun Rhee, Zhihua Wang:
A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems. VLSI-DAT 2018: 1-4

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