"An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training ..."

Chi Liu et al. (2022)

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DOI: 10.1109/VLSI-DAT54769.2022.9768058

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type: Conference or Workshop Paper

metadata version: 2022-05-23

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Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. VLSI-DAT 2022: 1-4

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