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"Low power pipelined SAR ADC with loading-free architecture."

Jia-Jhang Wu et al. (2014)

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DOI: 10.1109/VLSI-DAT.2014.6834906

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - https://dblp.org/rec/conf/vlsi-dat/WuCLHH14
Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, Guan-Ying Huang:
Low power pipelined SAR ADC with loading-free architecture. VLSI-DAT 2014: 1-4

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