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"Run-time self-tuning banked loop buffer architecture for power ..."

Antonio Artés et al. (2011)

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DOI: 10.1109/VLSISOC.2011.6081635

access: closed

type: Conference or Workshop Paper

metadata version: 2022-06-23

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Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor:
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. VLSI-SoC 2011: 136-141

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