"Simultaneous Placement and Buffer Planning for Reduction of Power ..."

Tudor Murgan et al. (2006)

> Home

Details and statistics

DOI: 10.1109/VLSISOC.2006.313251

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi/MurganMPBG06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/MurganMPBG06
Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner:
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. VLSI-SoC 2006: 302-307

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.