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"A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in ..."

Pierluigi Cenci et al. (2019)

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DOI: 10.23919/VLSIC.2019.8778176

access: closed

type: Conference or Workshop Paper

metadata version: 2020-04-03

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Pierluigi Cenci, Muhammed Bolatkale, Robert Rutten, M. Ganzerli, Gerard Lassche, Kofi A. A. Makinwa, Lucien J. Breems:
A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. VLSI Circuits 2019: 230-

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