Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC ..."

James Hudner et al. (2018)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2018.8502436

access: closed

type: Conference or Workshop Paper

metadata version: 2021-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/HudnerCCHNCEPLZ18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/HudnerCCHNCEPLZ18
James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. VLSI Circuits 2018: 47-48

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.