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"MN-Core - A Highly Efficient and Scalable Approach to Deep Learning."

Ken Namura et al. (2021)

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DOI: 10.23919/VLSICIRCUITS52068.2021.9492395

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-11

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  dblp key:
  - conf/vlsic/NamuraKAIKKWTKM21
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  - https://dblp.org/rec/conf/vlsic/NamuraKAIKKWTKM21
Ken Namura, Johannes Maximilian Kühn, Tohru Adachi, H. Imachi, H. Kaneko, T. Kato, Go Watanabe, Naoto Tanaka, S. Kashihara, Hiroshi Miyashita, Y. Tomonaga, Ryosuke Okuta, Takuya Akiba, Brian Vogel, S. Kitajo, F. Osawa, K. Takahashi, Y. Takatsukasa, K. Mizumaru, T. Yamauchi, J. Ono, A. Takahashi, Tanvir Ahmed, Y. Doi, K. Hiraki, J. Makino:
MN-Core - A Highly Efficient and Scalable Approach to Deep Learning. VLSI Circuits 2021: 1-2

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