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"Synchronous Test Generation Model for Asynchronous Circuits."

Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy (1996)

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DOI: 10.1109/ICVD.1996.489481

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/BanerjeeCR96
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/BanerjeeCR96
Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy:
Synchronous Test Generation Model for Asynchronous Circuits. VLSI Design 1996: 178-185

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