"Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, ..."

Shweta Chary, Michael L. Bushnell (2006)

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DOI: 10.1109/VLSID.2006.51

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Shweta Chary, Michael L. Bushnell:
Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 413-418

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