Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor."

Vivek Kumar et al. (2023)

> Home

Details and statistics

DOI: 10.1109/VLSID57277.2023.00067

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsid/KumarPDD23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/KumarPDD23
Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta:
FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. VLSID 2023: 1-6

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.