"VERSE: A Vector Replacement Procedure for Improving Test Compaction in ..."

Irith Pomeranz, Sudhakar M. Reddy (1999)

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DOI: 10.1109/ICVD.1999.745156

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Irith Pomeranz, Sudhakar M. Reddy:
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. VLSI Design 1999: 250-255

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