"Status Condition Analysis during Data Path Verification of Sequential ..."

Dipankar Sarkar (2000)

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DOI: 10.1109/ICVD.2000.812587

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Dipankar Sarkar:
Status Condition Analysis during Data Path Verification of Sequential Circuits. VLSI Design 2000: 70-75

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