"A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced ..."

Yesin Ryu et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830391

access: closed

type: Conference or Workshop Paper

metadata version: 2026-01-04

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Yesin Ryu, Young-Cheon Kwon, Jaehoon Lee, Sung-Gi Ahn, Jaewon Park, Kijun Lee, Yu Ho Choi, Han-Won Cho, Jae San Kim, Jungyu Lee, Haesuk Lee, Seung Ho Song, Je-Min Ryu, Yeong Ho Yun, Useung Shin, Dajung Cho, Jeong Hoan Park, Jae-Seung Jeong, Sukhan Lee, Kyounghwan Lim, Tae-Sung Kim, Kyungmin Kim, Yu Jin Cha, Ik Joo Lee, Tae Kyu Byun, Han Sik Yoo, Yeong Geol Song, Myung-Kyu Lee, Sunghye Cho, Sung-Rae Kim, Ji-Min Choi, Hyoungmin Kim, Soo Young Kim, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, SangJoon Hwang, JooYoung Lee:
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. VLSI Technology and Circuits 2022: 130-131

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