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"On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, ..."

Karel Heyse et al. (2014)

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DOI: 10.1007/978-3-319-05960-0_8

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Karel Heyse, Dirk Stroobandt, Oliver Kadlcek, Oliver Pell:
On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure. ARC 2014: 85-96

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