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"A switched-loop-filter PLL with fast phase-error correction technique."

Yongsun Lee et al. (2018)

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DOI: 10.1109/ASPDAC.2018.8297333

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-16

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  dblp key:
  - conf/aspdac/LeeSYC18
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  persistent URL:
  - https://dblp.org/rec/conf/aspdac/LeeSYC18
Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi:
A switched-loop-filter PLL with fast phase-error correction technique. ASP-DAC 2018: 307-308

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