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"A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale ..."

Ji-Wook Kwon et al. (2014)

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DOI: 10.1109/CICC.2014.6946034

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jong-Ho Kang, Seung-Tak Ryu:
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. CICC 2014: 1-4

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