Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"On timing yield improvement for FPGA designs using architectural symmetry ..."

Haile Yu, Qiang Xu, Philip Heng Wai Leong (2011)

> Home

Details and statistics

DOI: 10.1145/1950413.1950467

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/YuXL11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/YuXL11
Haile Yu, Qiang Xu, Philip Heng Wai Leong:
On timing yield improvement for FPGA designs using architectural symmetry (abstract only). FPGA 2011: 278

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.