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"Evaluating irregular memory access on OpenCL FPGA platforms: A case study ..."

Yingyi Luo et al. (2017)

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DOI: 10.23919/FPL.2017.8056827

access: closed

type: Conference or Workshop Paper

metadata version: 2017-10-11

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  - conf/fpl/LuoWYMMFC17
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Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello:
Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. FPL 2017: 1-4

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