"CPU-aware, process-level redundancy to tolerate faults in multi-core."

Hananeh Aliee, Hamid R. Zarandi, Alireza Tajary (2011)

Details and statistics

DOI: 10.1109/HPCSIM.2011.5999844

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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