"Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile ..."

Takahiro Hanyu (2013)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2013.6571796

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/Hanyu13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/Hanyu13
Takahiro Hanyu:
Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor. ISCAS 2013: 117-120

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.